While many integrated circuits today are digital, comprising memory, logic, digital signal processing, microprocessors, logic arrays, and so on, a number of products and electronic functions still rely on analog circuitry, either alone or combined with digital circuitry into mixed signal applications. Analog integrated circuits form a branch of semiconductor technology that is concerned with integrated circuits that operate in what is often referred to as the “analog” or “linear” circuit operating regime. In analog ICs, some of the integrated devices are used in power applications to switch currents, but there are other uses for analog devices as well, especially when operating as constant current sources or controlled current sources in voltage references, current mirrors, oscillators, and amplifiers. This branch of the semiconductor industry is in general sharply distinguished from the digital branch, in terms of the electrical characteristics of the devices, the voltages and currents that the devices must handle, and the processes and techniques that are used to manufacture the devices.
Typically, digital devices are subjected to low currents and voltages, and they are used to switch these low currents on and off, performing logical and arithmetic functions. The signal inputs to digital chips are generally themselves digital signals, and the power supply input generally constitutes a well regulated input with only a few percent maximum variation. All input and output pins are generally well behaved, staying within the designated supply voltage range, mostly emanating from the outputs of other digital ICs. Most outputs drive loads that are capacitive or resistive in nature and often only the inputs of other digital ICs.
Analog ICs, in contrast, must experience a far wider range of operating environments. First of all, many analog and power ICs are connected directly to the battery or power input of a product and are therefore subjected to a full range of potential over-voltage and noise conditions. In fact, the regulated supply used to power digital ICs is generally an analog voltage regulator IC protecting the digital IC from the variations in the raw power source, variations exceeding several tens of percents. Furthermore, the inputs to analog ICs often are themselves analog signals which may include noise mixed into the signal being monitored or detected. Lastly, the outputs of analog ICs often must drive high voltage or high current loads. These loads may include inductors or motors, causing the output pin of the IC to exceed the supply voltage or go below ground potential, and may result in the forward biasing of PN junctions leading to undesirable parasitic bipolar transistor conduction.
The technologies used to fabricate analog and power ICs, especially processes combining CMOS and bipolar transistors, may benefit both digital and analog ICs in performance and in chip size. But in most instances digital ICs use fabrication processes optimized to produce transistors that consume the smallest possible area, even if the ideality or performance of the semiconductor devices must suffer in order to reduce area. In analog and power ICs, the operating characteristics as well as the size are both important parameters, where one cannot be sacrificed completely at the expense of the other. Some characteristics especially beneficial to analog, mixed signal, and power ICs include:                Fabricating devices of different voltage ratings on a single chip, (including for MOSFET devices of different gate-to-source and drain-to-source voltage ratings and for bipolar transistors different collector-to-emitter voltage ratings),        Isolating devices from one another and from their common shared substrate, especially if they operate at different voltages or perform widely disparate functions within an IC,        Isolating a group of devices from a common substrate into an isolation pocket or tub so that the bias potential imposed on said devices can be maintained at a low voltage, while the entire pocket “floats” at a high voltage above the substrate potential,        Isolating a group of devices from a common substrate to prevent small signal noise from interfering from their proper circuit operation,        Suppressing the spread of minority carriers into the common substrate (parasitic bipolar conduction) from forward biased PN junctions,        Minimizing the possible effects of voltage drops and spatial variations in potential along the substrate (so called “ground bounce”) on other devices and circuits,        Integrating transistors whose output characteristics are optimized to operate as constant current sources with minimal voltage dependence, i.e. with flat output I-V characteristics (often described for bipolars as having a high Early Voltage VA, and for MOSFETs for having a high small-signal saturated output impedance ro),        Integrating high voltage transistors capable of “level-shifting” control signals to aforementioned “floating” pockets of low-voltage circuitry.        Integrating low-resistance MOSFETs for high current capable switches, especially with fast signal propagation throughout a large device array,        Integrating high current and/or high voltage devices capable of surviving limited durations of operation in avalanche breakdown without incurring permanent damage, degradation or immediate failure (also known as rugged devices),        Integrating large area passives such as high-value resistors, and large-area voltage-independent capacitors with a minimum use of silicon real estate,        Integrating precisions analog circuitry, especially accurate current sources, and temperature independent voltage references which vary little from wafer lot to wafer lot        
For these reasons, and others, the process technologies used to fabricate non-digital integrated circuits are unique, and oftentimes mix bipolar and CMOS devices into a single process. Merged bipolar-CMOS processes include names like BiCMOS (bipolar-CMOS), and CBiC (complementary bipolar-CMOS) processes. If a power MOSFET is also integrated, the power MOSFET may use the standard CMOS components, or may employ a DMOS device (the “D” in DMOS was originally an acronym for double diffused). The mix of bipolar, CMOS, and DMOS transistors into one process architecture is often referred to as a BCD process. Most of these processes require a complex process flow to achieve isolation between devices, especially when NPN or PNP bipolars are included.
The industry has adopted a fairly standard set of procedures in the manufacture of analog, bipolar-CMOS, BCD, and power applicable integrated devices. Typically, an epitaxial (epi) layer is grown on top of a semiconductor substrate. Dopants are often implanted into the substrate before the epi is grown. As the epi layer is formed, these dopants diffuse both downward into the substrate and upward into the epi layer, forming a “buried layer” at the interface between the substrate and the epi layer at the completion of the epi layer. The process is complicated by the fact that the buried layer implant must be diffused well away from the surface prior to epitaxial growth to avoid unwanted and excessive updiffusion of the buried layer into the epitaxial layer. This long pre-epitaxial diffusion is especially needed to avoid unwanted removal of the buried implant layer during the etch-clean that occurs at the beginning of epitaxial deposition (which removes the top layers of the substrate by etching to promote defect-free crystal growth).
Transistors and other devices are normally formed at or near the surface of the epi layer. These devices are typically formed by implanting dopants into the epi layer and then subjecting the substrate and epi layer to elevated temperatures to cause the dopants to diffuse downward into the epi layer. Depending on the dose of the implant, the diffusivity of the dopant, and the temperature and duration of the thermal process, regions of various sizes and dopant concentrations can be formed in the epi layer. The energy of these implants is generally chosen to penetrate through any thin dielectric layers located atop the area to be implanted, but not to penetrate deeply into the silicon, i.e. implants are located in shallow layers near the epitaxial surface. If a deeper junction depth is required, the implant is then subsequently diffused at a high temperature between (1000° C. to 1150° C.) for a period of minutes to several hours. If desired, these regions can be diffused downward until they merge with buried layers initially formed at the interface of the substrate and the epi layer.
There are numerous aspects of this standard fabrication process that impose limitations on the characteristics and variety of devices that can be formed in the epi layer. First, during the thermal process (sometime referred as an “anneal”) the dopants diffuse laterally as well as vertically. Thus, to cause the dopants to diffuse deeply into the epi layer, one must accept a significant amount of lateral diffusion. As a rule of thumb, the lateral diffusion or spreading is equal to about 0.8 times the vertical diffusion. Obviously, this limits the horizontal proximity of the devices to each other, since a certain horizontal spacing must be provided between the implants in anticipation of the lateral spreading that will occur during the anneal. This limits the packing density of the devices on the wafer.
Second, since all of the devices in a given wafer are necessarily exposed to the same thermal processes, it becomes difficult to fabricate devices having diverse, preselected electrical characteristics. For example, Device A may require an anneal at 900° C. for one hour in order to achieve a desired electrical characteristic, but an anneal at 900° C. for one hour may be inconsistent with the electrical characteristics required for Device B, moving or redistributing the dopants in an undesirable way. Once a dopant has been implanted, it will be subjected to whatever “thermal budget” is applied to the wafer as a whole thereafter, making dopant redistribution unavoidable.
Third, the dopant profile of the diffusions is generally Gaussian, i.e., the doping concentration is highest in the region where the dopant was originally implanted, typically near the surface of the epi layer, and decreases in a Gaussian function as one proceeds downward and laterally away from the implant region. Sometimes it may be desired to provide other dopant profiles, e.g., a “retrograde” profile, where the doping concentration is at a maximum at a location well below the surface of the epi layer and decreases as one moves upward towards the surface. Such retrograde profiles are not possible using an all-diffused process. Another desirable profile includes flat or constant dopant concentrations, ones that do not substantially vary with depth. Such profiles are not possible using an all-diffused process. Attempts have been made to produce such flat profiles using multiple buried layers alternating with multiple epitaxial depositions, but these processes are prohibitively expensive since epitaxy is inherently a slower, more expensive process step than other fabrication operations.
Fourth, deeper junctions produced by long diffusions require minimum mask features that increase in dimension in proportion to the depth of the junction and of the epitaxial layer to be isolated. So a 10 micron epitaxial layer requires an isolation region whose minimum mask dimension is roughly twice that of a 5 micron layer. Since thicker layers are needed to support higher voltage isolated devices, there is a severe penalty between the voltage rating of a device and the wasted area needed to isolate it. High voltage devices therefore have more area devoted to isolation, pack fewer active devices per unit area, and require larger die areas for the same function than lower voltage processes. Larger die area results in fewer die per wafer, resulting in a more expensive die cost.
Fifth, in epitaxial processes, the epitaxial layer thickness must be chosen to integrate the highest voltage device needed on a given chip. As explained previously, higher voltage devices requires deeper, less area-efficient isolation diffusions. These thick, wide-isolation diffusions are then required even in the lower voltage sections of the chip, wasting even more area. So in conventional processes, the highest voltage device sets the area efficiency of all isolated regions.
Sixth, many IC processes do not have the capability to integrate a voltage independent capacitor like poly-to-poly, poly-to-metal, or metal to poly, nor do they contain a high sheet resistance material for high value resistors.
FIGS. 1–6 illustrate some of the problems associated with various prior art devices.
FIG. 1A shows a conventional CMOS device that contains a P-channel MOSFET (PMOS) 101 and an N-channel MOSFET (NMOS) 102. PMOS 101 is formed in an N well 132; NMOS 102 is formed in a P well 134. N well 132 and P well 134 are both formed in a P substrate 130. The device also contains polysilicon gates 140 that are covered with a metal layer 142 such as a silicide to improve the conductivity of the gate. Sidewall spacers 146 are formed on the walls of gates 140, and in PMOS 101 these sidewall spacers allow the formation of P lightly-doped regions 144 adjacent the P+ source/drain regions 136, 138 to improve the breakdown characteristics of the device. Sidewall spacers 146 are formed by directionally etching an oxide layer from the horizontal surfaces of the device. P lightly-doped regions 144 are aligned to the gate 140 and P+ source/drain regions 136, 138 are aligned to sidewall spacers 146. P lightly-doped regions 144 are implanted before the formation of sidewall spacers 146, and P+ source/drain regions 136, 138 are implanted after the formation of sidewall spacers 146. Each of these steps requires a mask. P+ source/drain regions 136, 138 are contacted by a metal layer 148 with a barrier metal layer 150, typically TiN (titanium-nitride) being formed at the interface with P+ source/drain regions 136, 138.
NMOS 102 contains similar components with opposite polarities. PMOS 101 and NMOS 102 are separated by a field oxide layer 152. Normally there is a field dopant (not shown) under the field oxide layer. In some cases the surface concentration of P well 134 or N well 132 can be sufficiently high to raise the field threshold between adjacent NMOS or PMOS devices to a value greater than the supply voltage, and to maintain the minimum threshold criteria despite normal variations in doping, oxide thickness, or operating temperature.
A problem with this device is that NMOS 102 is not isolated from the P substrate 130, since there is no PN junction between P substrate 130 and P well 134. P well 134 cannot float. Instead there is simply a resistive connection between P substrate 130 and P well 134. Noise can be coupled into NMOS 102. Current having nothing to do with the circuit connection of NMOS 102 can flow from substrate 130 into P well 134. Since every MOSFET contains four electrical terminals; a gate, a source, a drain, and a back-gate (also known as the channel or body of the device), then by this nomenclature the body of NMOS 102 comprising P well 134 is directly tried to the substrate (herein referred to as electrical ground) and cannot be biased to a potential above the grounded substrate 130. Since the P well 134 is grounded, any bias on the source pin of NMOS 102, will raise its threshold and degrade the MOSFET's performance.
In contrast, N well 132 can be reverse-biased relative to P substrate 130, isolating the PMOS 101 from the substrate potential. Since the device is isolated, the source 148/136 of the PMOS can be shorted to N well 132, the body of the PMOS, and allow operation above ground without degrading the PMOS's electrical performance.
Since N well 132 has a limited amount of doping present in such well region, the PMOS may not always operate in an ideal manner, especially due to parasitic bipolar conduction. Specifically, N well 132 forms a parasitic PNP bipolar transistor (PNP) between the P+ source/drain regions 136, 138 and the P substrate 130. If either the PN junction between P substrate 130 and N well 132, or (more likely) the PN junction between one of the P+ source/drain regions 136, 138 and P substrate 130, becomes forward-biased, the parasitic PNP could turn on and conduct unwanted current into P substrate 130. Also, there are typically parasitic NPN transistors elsewhere in the IC chip (e.g. comprising N well 132, P substrate 130 and any other N+ region located within P substrate 130), and these NPNs can combine with the PNP in N well 132 to produce a latch-up condition (parasitic thyristor action).
In digital applications these problems may not be significant. Typically the PN junctions do not become forward-biased. The wells are heavily doped and there is no particular concern with having high breakdown voltages or a flat output current characteristic when the transistor is turned on.
PMOS 101 and NMOS 102 work reasonably well in a circuit of the kind shown in FIG. 1B, where the source and body of PMOS 101 are both tied to Vcc, and the source and body of NMOS 102 are both tied to ground. Thus the body-drain junctions of both devices are reverse-biased so long as the drain potential of PMOS 101 and NMOS 102 remains at a voltage equal to or intermediate to the ground and Vcc supply rails.
The situation is different, however, where the devices are formed in or operate as a circuit of the kind shown in FIG. 1C. There the body of NMOS 102 is resistively tied to ground and the source is typically shorted to ground and the device therefore cannot be isolated. Also, there is a NPN bipolar transistor (dashed lines) between the source and the drain. In PMOS 101, the diode that represents the PN junction between P substrate 130 and N well 132 forms a part of the parasitic PNP transistor (also shown in FIG. 1A) between P substrate 130 and P+ region 138. As a result, the devices cannot be floated in circuit that is not reasonably near the ground potential, without risk of the PNP conducting or exhibiting snapback breakdown, especially at high temperatures.
A modified structure that has been used in the power MOSFET area to extend the voltage range of the devices is shown in FIG. 2A. The voltage range of PMOS 103 has been extended by forming an extended P− “drift” region 156 adjacent the P+ drain region 154 in N well 132. The current flows from the P+ source region 162 and through N well 132 and into P drift region 156 and P+ drain region 154. However, PMOS 103 still has the same parasitic PNP transistor (dashed lines) described before for PMOS 101.
In NMOS 104, P well 134 has been limited to enclose only the N+ source region 160 and the P+ body contact region 162, and an N well 158 has been formed adjacent to and enclosing N+ drain region 164. Gate 166 overlaps the field oxide region 152 and onto thin gate oxide (active region) overlapping the surface channel formed by the N sidewall spacer of N+ 160 acting as source, P well 134 acting as body, and N well 158 acting as drain of a high voltage N-channel MOSFET 104. In NMOS 104, the current flows from the N+ source region 160 and through P well 134 (the channel region) and N well 158 to N+ drain region 164. N well 158 acts as an N− drift region which, if it is doped lightly enough will deplete and extend the voltage range of NMOS 104.
NMOS 104, however, has an additional problem that is illustrated in FIG. 2B. If NMOS 104 becomes saturated, as it often does during switching, in the constant-current mode, N well 158 may become substantially depleted. When the electrons emerge from channel 168, they enter an area of N well 158 located between field oxide region 152 and P well 134, where the strength of the electric field is high (as indicated by the equipotential lines II), especially adjacent the field oxide region 152 and the thin gate oxide portion underlying gate 166. As result, impact ionization may occur, generating hot carriers, particularly adjacent field oxide region 152 where the defects associated with the LOCOS process are present. If N well 158 is substantially depleted, the current is not constrained within N well 158. Thus, if NMOS 104 is driven into saturation, the hot carriers may rupture the gate oxide and destroy the thin oxide underlying gate 166.
FIG. 2C is a graph of the drain current ID through NMOS 104 as a function of the drain-to-source voltage VDS, Curve A shows the situation when the device is turned off. The ideal operation is for the current to remain at zero until breakdown occurs and then rise with VDS remaining essentially constant (curve A1), the device acting as a voltage clamp. Where there are parasitic bipolar transistors, or where impact ionization occurs, so many carriers are generated the voltage collapses or “snaps back” after breakdown (curve A2) and if the current rises too much the device will be destroyed. As shown by curve B, a similar result can occur when NMOS 104 is turned on. Hot carriers are generated by the channel current through the device and these hot carriers can cause the device to snap back in what is sometimes referred to as a safe operating area (SOA) failure. The fact that the doping concentrations and profiles cannot be controlled very accurately, because the dopants are being thermally diffused, makes these problems worse, especially considering that Gaussian dopant profiles have their highest concentrations at the silicon surface, where the electric fields are also highest.
FIG. 2D illustrates a problem that can occur with PMOS 103 as a result of the inability to control the doping profile of N well 132. Even though PMOS 103 is isolated from P substrate 130, if the source-body voltage VDD gets to be too far above ground (e.g., 12V in a 5V device, 18V in a 12V device, etc.), the depletion region will spread upward in N well 132 towards the surface of the substrate. Since the doping profile of N well 132 cannot be controlled, the diffusion times must be increased to drive the PN junction far into the substrate to prevent the depletion region from reaching the surface of the substrate. Normally, there is a compromise. The N well 132 is not as deep as would be desirable, and the depletion does reach back into the N well. This narrows the width of the parasitic bipolar transistor in PMOS 103, since the actual net electrical width of the base is the depth of the PN junction between N well 132 and P substrate 130, less the width of the depletion region within N well 132.
Moreover, if the junction between N well 132 and P substrate 130 ever becomes even slightly forward-biased, the device will have a tendency to snap back, because the base of the parasitic bipolar transistor between P substrate 130 and P+ drain 154 (dashed lines) has a very resistive contact and therefore the parasitic bipolar will experience what is essentially an “open-base” breakdown (BVCEO). This breakdown voltage is much lower than the normal reverse-bias junction breakdown between N well 132 and P substrate 130. If this happens the device will most likely be destroyed. If PMOS 103 becomes saturated, hot carriers will be generated that may also lead to this phenomenon.
Probably the biggest single problem with PMOSs 101, 103 is that they are not floating, meaning they cannot be biased at a high N well-to-P substrate potential without snapping back. Similarly, one of the biggest problems with NMOSs 102, 104 is that they are not floating, meaning their body connection cannot be biased above the substrate potential at all. This limits greatly the types of circuits in which they can be used.
FIG. 3 illustrates how this problem occurs in an illustrative power conversion circuit 105. Circuit 105 includes low-side circuitry 170, which would be biased near ground (e.g., 5V or less above ground), and high-side circuitry 172, which could float 20V or 30V above ground (the substrate). MOSFET M1 would typically be a high-voltage N-channel device that sends a signal through a resistor R1 to high-side circuitry 172 and would have a breakdown voltage of 20V to 30V, even though the input signal at the gate of M1 might only be 5V. MOSFET M2 would be a high-voltage P-channel device that level-shifts a signal through a resistor R2. MOSFETs M3 and M4 constitute a 5V or 12V CMOS pair that drives the gate of an N-channel output high-side MOSFET M7. The source of MOSFET M3 needs to float 20V or 30V above the substrate, but MOSFETs M3 and M4 are themselves low-voltage devices. This minimizes the area they occupy on the chip.
MOSFETs M5 and M6 are a CMOS pair similar to MOSFETs M3 and M4, but the source of MOSFET M5 is connected to ground. MOSFETs M5 and M6 drive the gate of an N-channel output low-side MOSFET M8.
Bootstrap capacitor C1 powers the floating high-side circuit and floats above ground. The voltage across capacitor C1 VBootstrap is 5V. When output MOSFET M7 is turned on, raising the lower terminal of capacitor C1 to 20V, diode D10, which is used to charge capacitor C1, must block approximately 25V (i.e., VDD+VBootstrap).
Thus, in a circuit such as circuit 105, one must have the flexibility to include high-voltage devices and dense, floating low-voltage devices on a single chip. The devices shown in FIGS. 1A and 2A do not meet the needs of circuit 105 shown in FIG. 3.
FIG. 4A shows the prior art's answer to this problem, although it represents a step backwards technologically. An N-type epitaxial (N-epi) layer 176 is grown on a P substrate 174. PMOS 107 is formed in N-epi layer 176, and NMOS 106 is formed in a P well 178 in N epi layer 176. Thus NMOS 106 and PMOS 107 constitute a CMOS pair that floats above P substrate 174.
The chip also includes an N-channel lateral DMOS 108 that is isolated from P substrate 174 by the junction between N-epi layer 176 and P substrate 174 and from the CMOS pair by a P-type isolation diffusion 180. An N buried layer 184 provides isolation for the CMOS pair.
One problem with this structure is that it requires long diffusions. For example, P isolation diffusion 180 must be diffused through the entire N-epi layer 176 to reach P substrate 174, and P body 182 of lateral DMOS 108 likewise requires a long diffusion at a high temperature (e.g., 12 hours at 1100° C. or more).
Moreover, to align P body 182 to gate 186 of lateral DMOS 108 requires that gate 186 be formed before P body 182 is implanted. The CMOS pair typically has a threshold adjust implant that would be performed before the polysilicon gates 188 are deposited. The long anneal required to diffuse P body 182, however, would render useless any threshold adjust implant that was previously performed in the CMOS pair. The only way to avoid this problem would be to deposit the gate 186 of lateral DMOS before the gates 188 of the CMOS, but this would add considerable complexity to the process.
The devices typically have a channel length of 0.8–2.0 μm rather than 0.35 μm. One could use a 0.35 μm process to fabricate this structure but the number of masking steps could become excessive. The number of steps to form the isolation structures would be added to the steps for the 0.35 μm process and the threshold adjust. Normally the prior art has settled for lower density and less complexity in order to get this isolation capability. Moreover, the effort to reduce the size of CMOS devices and the resulting benefit in reduced die size are mostly lost when the large wasted area of isolation diffusions 180 is considered.
FIG. 4B shows N-channel quasi-vertical DMOSs 109 that are formed in N-epi layer 176 and are isolated from P substrate 174. In each device, the current flows from N+ source region 192, laterally through a channel in P body 194 under gate 190, downward in N-epi layer 176 to N buried layer 196, laterally in N buried layer 196, and upward through N+ sinker 198. An advantage of the devices is that the current is pinched off by spreading depletion regions between the P bodies when the devices are reverse-biased, and this protects the gate oxide layer. On the other hand, the on-resistance of the devices is increased by the distance that the current must flow through the N buried layer 196. To keep this resistance within acceptable limits N+ sinkers must be positioned periodically and frequently between the DMOSs, and this reduces the packing density of the chip. The higher the off-state blocking voltage BVDSS of such a DMOS device, the deeper N+ sinker diffusion 198 and P isolation diffusion 180 must be driven, wasting more die area for such deep and wide diffused regions.
FIG. 4C shows an NPN transistor (NPN) 110 that can be formed in the same process. The base 141 of NPN 110 would typically be formed by the same P diffusion as P body 182 N-channel LDMOS 108 (FIG. 4A) and therefore may not be optimal. The current characteristics of NPN 110 are generally quite good, but it must be large to accommodate the N+ sinker 143 and deep P isolation diffusion 147.
In high-voltage PMOS 111, the parasitic bipolar between P substrate 174 and N+ source region 151 is suppressed by N buried layer 149. To obtain the high-voltage feature, however, N epi layer 176 must be 6 μm to 10 μm thick and this further increases the length of the diffusion required for N+ sinker 143 and P isolation region 147. A greater vertical diffusion means a greater horizontal diffusion, so this further increases the size of the device.
FIG. 5A shows an alternative technique of forming an isolation region that limits somewhat the length of the diffusion and helps reduce lateral spreading of such deep diffusions. A P isolation region 153 is implanted near the surface of N-epi layer 176 (after epitaxial growth), and a P buried layer 155 is formed at the interface of N-epi layer 176 and P substrate 174 (prior to epitaxial growth). During the implant anneal, P isolation region 153 diffuses downward and P buried layer 155 diffuses upward until they merge somewhere in the middle of N-epi layer 176.
This process also raises the possibility of fabricating an isolation structure that includes a P buried layer 159 on top of an N buried layer 157, as shown in FIG. 5A. A relatively slow-diffusing dopant such as antimony or arsenic can be used to form N buried layer 157, and a relatively fast-diffusing dopant such as boron can be used to form P buried layer 159. Buried layers 157 and 159 are heavily doped, and the dopants must be driven deep into P substrate 174 to prevent them from coming out during the growth of N-epi layer 176. This is a highly variable process that is difficult to control. Furthermore, P isolation layer 153 must be aligned to PBL region 157 through the entire thickness of epitaxial layer 176. It is difficult to guarantee good alignment with this procedure, requiring extra spacing to be included in the design rules of a device and wasting silicon area.
This process does permit the fabrication of a fully isolated PNP, however, as shown in FIG. 5B. In PNP 112 an N buried layer 161 and a P buried layer 165 are formed at the interface between P substrate 174 and N-epi layer 176. N buried layer 161 is contacted via N+ sinkers 163, and P buried layer 165 and P isolation region 167 become the collector of PNP 112. PNP 112 is isolated from adjacent devices by P isolation regions 171, which are diffused downward to merge with up-diffusing P buried layers 169. P buried layers 169 and PBL 165 are generally the same P buried layer.
The use of a P buried layer can also help overcome the “hot carrier” problem described in connection with FIG. 2B. As shown in FIG. 5C, P buried layer 173, formed under the P body 134 of NMOS 104, “squeezes” the depletion regions back into the area directly under field oxide layer 152, where the breakdown fields are higher and more voltage can be tolerated, and therefore reduces the strength of the electric field at the surface of N-epi layer 176 under gate 166.
If the charge Q in N-epi layer 176 is chosen to be in the range of 1.0–1.3×1012 atoms cm−2, then N-epi layer 176 fully depletes before it breaks down, and a much higher voltage can be applied to the device (e.g., hundreds of volts). This is known as a “resurf” device in the prior art. The charge Q is equal to the doping concentration times the depth of N-epi layer 176 (strictly speaking the charge is equal to the integral of the concentration integrated over the thickness of the epitaxial layer).
FIG. 6A shows a different approach to the problem. Here, a P-epi layer 179 is grown on P substrate 174. An isolated P pocket 187 is formed in P-epi layer 179 by down-diffusing N isolation regions 185, up-diffusing N buried layers 183, and forming an N buried layer 181. N regions 185 and N buried layers 183 are doped with a relatively fast-diffusing dopant such as phosphorus, whereas N buried layer 181 is formed of a relatively slow-diffusing dopant such as antimony or arsenic. As a result, an “N tub” is formed surrounding P pocket 187. An N well 190 and optionally a P well (dashed lines) are formed in isolated P pocket 187. A PMOS 113 is formed in N well 191, and an NMOS 114 is formed in P pocket 187 (or in the P well). PMOS 113 and NMOS 114 are similar to PMOS 101 and NMOS 102, shown in FIG. 1A, except that they may or may not include sidewall spacers. Outside the “N tub” a high-voltage lateral DMOS (HV LDMOS) 115 is fabricated, similar to NMOS 104 shown in FIG. 2A, except that a P body diffusion 193 may be used in place of the P well 134 (dashed lines) and an N field doping 195 under field oxide layer 152 serves as the “drift” region of HV LDMOS 115. HV LDMOS 115 does not have a P buried layer similar to P buried layer 173 shown in FIG. 5C to reduce the strength of the electric field under the gate.
In fabricating PMOS 113, P-epi layer 179 must be thick enough to ensure that, taking into account the variability in the thickness of P-epi layer 179, N buried layer 181 does not overlap N well 191 Otherwise, N buried layer 181, which is heavily doped, may influence the electrical characteristics of PMOS 113. Another approach is shown in FIG. 6B, where instead of having two separate phosphorus buried layers 183, a single phosphorus N buried layer 197 up-diffuses and merges with N isolation regions 185. The arsenic or antimony N buried layer 181 remains well below N well 191, but the up-diffusing phosphorus merges into N well 191. Because the doping concentration of the portion of N buried layer 197 that overlaps N well 191 is low, the electrical characteristics of PMOS 113 are not significantly effected by N buried layer 197.
FIG. 6B also shows that an NPN 116 can be fabricated in the same process. The base of NPN 116 is wider than the base of NPN 110, shown in FIG. 4C, because the base includes some of P-epi layer 179 rather than just the P body diffusion 141. Since the width of P-epi layer 179 is variable, NPN 116 is not as reproducible as NPN 110.
FIG. 6C summarizes the options for the fast-diffusing (phosphorus) and slow-diffusing (arsenic or antimony) N buried layers in the embodiments of FIGS. 6A and 6B. The fast and slow-diffusing N buried layers can be separate, as shown on the left side of FIG. 6C, or they can be superimposed on one another, perhaps using the same mask, as shown on the right side of FIG. 6C. In both cases, the fast diffusant (labeled U1 as an acronym for up isolation) extends both above and below the vertical extent of the slow diffusing NBL.
The devices shown in FIGS. 1A–1C, 2A–2D, 3, 4A–4C, 5A–5C, 6A–6C share a common set of problems. They generally require long thermal cycles to diffuse dopants to desired depths in a substrate or epitaxial layer. These diffusions cause redistribution of every dopant present within the silicon at the time of the diffusion, including devices where it would be preferable to prevent or limit dopant diffusion. For example, any well diffusion cycle performed after field oxidation occurs causes the dopant concentration at the silicon surface directly under the field oxide to decline, lowering the “field threshold” of parasitic surface MOSFETs formed between adjacent like-type devices. This unwanted redistribution may allow a parasitic PMOS to be formed between adjacent PMOSs sharing a common N well, or parasitic NMOS conduction between adjacent NMOSs sharing a common P well. To raise the field threshold and counter the adverse affects of diffusion, a higher field threshold implant is required. A higher implant dose, however, raises the surface concentration leading to lower surface breakdowns and higher surface fields.
Moreover, a higher surface concentration is also subject even greater diffusion due to a higher concentration gradient. To avoid these effects, the possible process architectures are limited to sequences where the dopants that must not diffuse must be introduced late in the process, after gate oxidations, field oxidations, well diffusions, etc. Such a limitation imposes many restrictions in the device type and device optimization possible.
High temperature diffusions also generally produce Gaussian dopant profiles in the resulting wells or other regions. One cannot fabricate regions having predetermined yet arbitrary, non-Gaussian dopant profiles. For example, a retrograde profile having a higher subsurface concentration than its surface concentration cannot be performed using purely diffused techniques. Such diffusions (and diffusions in general) are difficult to accurately control, and the actual results may vary widely from what is desired especially when the variability from wafer-to-wafer (from a single wafer batch ) and variability from wafer-batch to wafer-batch (so called “run-to-run variation”) are considered. The variability comes from poor temperature control and from dopant segregation occurring during oxidation.
Moreover, the diffusions, while intended primarily to introduce dopants deeper into the substrate, also spread the dopants laterally, and this increases the size of the devices, in some cases by substantial amounts.
To the extent that an epitaxial layer is used to fabricate the devices, these effects are further magnified by the effects of growing the epitaxial layer. Until now, the need for epitaxy has been virtually mandated by the integration of fully-isolated “analog quality” bipolars (i.e. excluding digital- and RF-optimized bipolars). Yet epitaxy remains the single most expensive step in wafer fabrication, making its use undesirable. Variability in epitaxial thickness and in concentration compound device optimization, and the epitaxial process necessarily occurs at a high temperature, typically over 1220 C. Such high-temperature processing causes unwanted updiffusion of the substrate in some regions of an IC, and of buried layers in other regions. The updiffusion produces a thinner epitaxial layer than the actual grown thickness, meaning added deposition time and thickness must be used to offset the updiffusion, making the epi layer as deposited thicker than it otherwise would need to be. Isolating a thicker epitaxial layer requires even longer diffusion times for the isolation diffusion structure, leading to excessively wide features.
In the event that multiple operating voltages are present within the same chip, the epitaxy needs to be selected for the maximum voltage device. The isolation width is then larger than necessary in sections of the IC not utilizing the higher voltage components. So, in essence, one component penalizes all the others. This penalty leads to poor packing densities for low voltage on-chip devices, all because of one higher voltage component. If the higher voltage device is not used, the wasted area lost to high voltage isolation (and related design-rule spacing) cannot be reclaimed without re-engineering the entire process and affecting every component in the IC. Such a process is not modular, since the addition or removal of one component adversely affects all the other integrated devices.
Accordingly, there is a clear need for a technology that would permit the fabrication of an arbitrary collection of optimized transistors or other devices, closely packed together in a single semiconductor wafer, fully isolated, in a modular, non-interacting fashion.